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Verification challenges

Post time:  2008-10-21
 

Author:joyn

Points:  10

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Can you kindly help me with some insights on various verification challenges. Also how can deal the same with some complex SoCs
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Reply: Verification challenges

Post time:  2008-10-24
 

Author:Editorial Team

Points:  300

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See Accelerating verification closure for complex SoCs, IPs published today.
You can find more articles on verification with a simple keyword search: http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/verification.HTM.
 
 
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Reply: Verification challenges Post time:  2008-12-22
 

Author:1229947988462

Points:  15

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You can find further information here:
www.thinkverification.com
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More on verification Post time:  2009-03-20
 

Author:News Team

Points:  11728

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Hi all,
You can find more on verification in The File on EDA. Read it now!
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Reply:Verification challenges Post time:  2009-03-23
 

Author:eetengr

Points:  135

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"Challenges in Verification" is quite a broader term. Depending on the perspective one is looking from, the challenges differ. Some of the challenges -
An Engr - Comprehensivley verifying a unit & ensuring reusability at system level.
An Architect - Ensuring the TB architecture provides enough capabilities for engr. to achieve verification goals while reusing the efforts across unit to system level & across programs. If it is an IP and reuse become all the more important.
A Methodology guy - Ensuring the latest & efficient methodologies are deployed to enable architect and engr achieve their goals.
A CAD guy - Look out for tools that can support methodolgies defined by the team.
A Manager - Keeping a top level view on the progress of the verification.

SOC involves lot of reuse so challenges involved are multifold.
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